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| EPL43102 43 Com / 102 Seg LCD Driver Product Specification DOC. VERSION 1.8 ELAN MICROELECTRONICS CORP. January 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation Copyright (c) 2006 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 2 3 4 5 6 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Applications............................................................................................................... 2 Pin Assignment ......................................................................................................... 2 4.1 Pad Coordinates..................................................................................................4 Block Diagram ........................................................................................................... 6 Pin Description.......................................................................................................... 7 6.1 6.2 6.3 6.4 7 Power Supply ......................................................................................................7 LCD Driver Supply...............................................................................................7 System Control....................................................................................................8 MPU Interface .....................................................................................................9 6.5 LCD Driver Output.............................................................................................10 Function Description ...............................................................................................11 7.1 7.2 System Interface ...............................................................................................11 MPU Interface ...................................................................................................11 7.2.1 7.2.2 Chip Select ........................................................................................................11 Selecting the Interface Type..............................................................................12 Display Data RAM .............................................................................................14 Programmable Duty Ratio.................................................................................16 Display Data Latch Circuit .................................................................................18 Shift Register Circuit..........................................................................................18 Common Driver Circuit ......................................................................................21 Segment Driver Circuit ......................................................................................21 LCD Driving Waveform......................................................................................22 Voltage Converter Circuits.................................................................................24 Voltage Regulator Circuits.................................................................................24 Voltage Follower Circuits...................................................................................26 Oscillator ...........................................................................................................28 /DOF Pin Description.........................................................................................28 Display Timing Generator Circuit ......................................................................28 Oscillator Frequency .........................................................................................29 7.3 Data Transfer.....................................................................................................13 7.3.1 7.3.2 7.4 LCD Driver Circuits............................................................................................18 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 Internal Power Circuits ......................................................................................23 7.5.1 7.5.2 7.5.3 7.6 LCD Display Circuits .........................................................................................27 7.6.1 7.6.2 7.6.3 7.6.4 7.7 Reset Circuit......................................................................................................29 Product Specification (V1.8) 01.20.2006 iii Contents 8 Instruction Description ........................................................................................... 30 8.1 8.2 8.3 8.4 Read Display Data ............................................................................................31 Write Display Data.............................................................................................31 Read Status.......................................................................................................32 Set Duty Ratio (Two-Byte Instruction) ...............................................................32 8.4.1 8.4.2 Set Duty Ratio Mode (First Instruction) .............................................................32 Set Duty Ratio Register (Second Instruction) ...................................................32 Set CL Frequency Select Mode (First Instruction) ............................................33 Set CL Frequency Select Register (Second Instruction) ..................................33 Set the LCD Bias Select Mode (First Instruction) .............................................33 Set the LCD Bias Select Register (Second Instruction)....................................34 8.5 Set Display Clock CL Frequency (Two-Byte Instruction)...................................33 8.5.1 8.5.2 8.6 Select LCD Bias (Two-Byte Instruction) ............................................................33 8.6.1 8.6.2 8.7 8.8 8.9 Display On/Off ...................................................................................................34 Initial Display Line .............................................................................................34 Electronic Contrast Control Set (Two-Byte instruction) .....................................34 8.9.1 8.9.2 Set Contrast Control Mode (First Instruction) ...................................................35 Set Contrast Control Register (Second Instruction)..........................................35 8.10 Set Page Address..............................................................................................35 8.11 Set Column Address..........................................................................................35 8.12 ADC Select........................................................................................................36 8.13 Inverse Display On/Off ......................................................................................36 8.14 Entire Display On/Off.........................................................................................36 8.15 Set Modify-Read................................................................................................36 8.16 Reset Modify-Read............................................................................................37 8.17 Reset .................................................................................................................37 8.18 SHL Select.........................................................................................................37 8.19 Power Control....................................................................................................38 8.20 Regulator Resistor Select..................................................................................38 8.21 Set Status Indicator (Two-Byte Instruction) .......................................................38 8.21.1 Set Status Indicator Mode (First Instruction) .....................................................38 8.21.2 Set Status Indicator Register (Second Instruction) ...........................................39 8.22 Power Save (Compound Instruction) ................................................................39 8.22.1 Sleep Mode .......................................................................................................39 8.22.2 Standby Mode ...................................................................................................40 9 Application Information .......................................................................................... 41 9.1 9.2 Instruction Procedure Examples .......................................................................41 9.1.1 Initial Setup........................................................................................................41 Program Examples............................................................................................43 iv * Product Specification (V1.8) 01.20.2006 Contents 10 Electrical Characteristics ....................................................................................... 46 10.1 Absolute Maximum Ratings...............................................................................46 10.2 Recommended Operating Conditions ...............................................................46 10.3 DC Characteristics ............................................................................................47 10.4 AC Characteristics.............................................................................................49 10.5 80-Family MPU Read/Write Timing Characteristics ..........................................50 10.6 68-Family MPU Read/Write Timing Characteristics ..........................................51 Pin Configuration .................................................................................................... 52 MPU Interface .......................................................................................................... 55 Application Circuits ................................................................................................ 57 11 12 13 Product Specification (V1.8) 01.20.2006 v Contents Specification Revision History Doc. Version 0.1 0.2 0.3 0.4 1. 0.5 2. 3. 1.1 1.2 1.3 1.4 1.5 1. 1.6 2. 1. 1.7 2. 1. 2. 1. 2. Revision Description Initial version Added 1/3 and 1/3.5 bias Added one more VDD and VSS pad. Modified the Pad sequence and configuration. Modified the DC and AC characteristics. Added pin configuration Added program example Modified the DC characteristics Modified the operating temperature range from -30 to 80C Added COG package Added TEST pin description Modified the reading timing of /WR Adjusted the Data RAM arrangement Modified the table on the relationship between duty ratio and common output Modified the A0 voltage level of Display ON/OFF instruction Added a Note on the M/S description under System Control section. Modified the table for Common and Segment Driver Circuits. Modified the COG part no. to EPL43102GH Modified the TEST pin description 09/07/2001 01/06/2003 04/25/2003 08/04/2003 12/29/2003 07/25/2001 Date 11/20/2000 02/15/2001 03/02/2001 07/17/2001 02/27/2004 08/18/2004 1.8 01/20/2006 vi * Product Specification (V1.8) 01.20.2006 EPL43102 43 Com / 102 Seg LCD Driver 1 General Description The EPL43102 is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It can be interfaced with the MPU via serial or 8-bit interface. It contains 43 common and 102 segment driver circuits. With one chip, it is possible to drive a graphic display system with a maximum of 102 x 43 dots. 2 Features Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 102 x 43 = 4386 bits 145 LCD Drivers : 102-seg segment drivers, 42-common drivers and 1-icon Serial Interface (SPI) or 8-Bit Parallel Interface Mode (80-series, 68-series MPU) On-chip oscillator circuit Multi-chip operation (Master, Slave) available Programmable Duty Ratio : Duty Ratio 1: 42 (+ ICON) 1: 36 (+ ICON) 1: 32 (+ ICON) 1: 24 (+ ICON) 1: 16 (+ ICON) 1: 8 (+ ICON) Note: ICON = "0" : Pin disable ICON = "1" : Pin enable Common 42 (+ ICON) 36 (+ ICON) 32 (+ ICON) 24 (+ ICON) 16 (+ ICON) 8 (+ ICON) Segment 102 102 102 102 102 102 Selectable LCD driving bias level: 1/3, 1/3.5, 1/4, 1/4.5, 1/5, 1/5.5, 1/6, 1/6.5, 1/7, 1/7.5, 1/8 bias Selectable LCD display clock frequency Electronic contrast control functions (64 steps) Built-in Instruction Set: Display data read/write, Display on/off, Inverse display, Page address set, Common address set, LCD display contrast control, Set Sleep mode, Standby mode, etc. Operating Voltage range: Supply voltage: 2.2 to 5.5 V LCD driving voltage: 4.0 to 15.0 V Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) *1 EPL43102 43 Com / 102 Seg LCD Driver Package (Ordering information): Part Number EPL43102H EPL43102GH Package Bare die Gold bumped die Description NA NA Package Information Page 2 Page 2 Note: The EPL43102 series has the following sub-codes, depending on their shapes. H: Bare chip (Aluminum pad without bump); GH: Gold bumped chip F: COF package; T: TAB (TCP) package Example: EPL43102AGH EPL43102: Elan number; A: Package Version; GH: Gold bumped chip 3 Applications Organizer Scientific calculator Graphic pager Electronic Dictionary Cellular phone Handy Terminals (PDA) 4 Pin Assignment 188 180 170 160 150 140 130 120 110 100 95 10 20 30 40 50 60 70 80 90 1 94 Note: With the Elan logo at the center (as shown in the figure) and DDRAM (black color) on the right side, Pin 1 is at the bottom left corner. Figure 4-1 Pin Configuration 2* Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Item Chip size Pad No. 1~15, 80~94 95~109,174~188 16~79 110~173 1~15, 80~94 Size X 8440 95 85 85 75 82 72 525 25 All Pad 17 3 (within die) 13 Die center 150 150 147 147 Y 1790 Unit Pad Pitch Pad Size (EPL43102H) Al pad 95~109,174~188 16~79 110~173 1~15, 80~94 m Bump Size (EPL43102GH) Au pad Die thickness Bump Height Minimum Bump Gap Coordinate Origin 95~109,174~188 16~79 110~173 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 3 EPL43102 43 Com / 102 Seg LCD Driver 4.1 Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COMI1 VDD VDD C1+ C1C3 C4 C2C2+ VOUT V0 V1 V2 V3 V4 VR GND GND MS PS FR C86 /DOF CLS CL OSC FRS IRS /RES X -4095.0 -4000.0 -3905.0 -3810.0 -3715.0 -3620.0 -3525.0 -3430.0 -3335.0 -3240.0 -3145.0 -3050.0 -2955.0 -2860.0 -2765.0 -2675.0 -2590.0 -2505.0 -2420.0 -2335.0 -2250.0 -2165.0 -2080.0 -1995.0 -1910.0 -1825.0 -1740.0 -1655.0 -1570.0 -1485.0 -1400.0 -1315.0 -1230.0 -1145.0 -1060.0 -975.0 -890.0 -805.0 -720.0 -635.0 -550.0 -465.0 -380.0 -295.0 -210.0 -125.0 -40.0 45.0 130.0 215.0 Y -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 Pad No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol D7 D6 D5 D4 D3 D2 D1 D0 CS2 /CS1 A0 /WR /RD TEST COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMI2 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 X 300.0 385.0 470.0 555.0 640.0 725.0 810.0 895.0 980.0 1065.0 1150.0 1235.0 1320.0 1405.0 1490.0 1575.0 1660.0 1745.0 1830.0 1915.0 2000.0 2085.0 2170.0 2255.0 2340.0 2425.0 2510.0 2595.0 2680.0 2770.0 2865.0 2960.0 3055.0 3150.0 3245.0 3340.0 3435.0 3530.0 3625.0 3720.0 3815.0 3910.0 4005.0 4100.0 4100.0 4005.0 3910.0 3815.0 3720.0 3625.0 Y -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 -742.5 742.5 742.5 742.5 742.5 742.5 742.5 4* Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG57 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 X 3530.0 3435.0 3340.0 3245.0 3150.0 3055.0 2960.0 2865.0 2770.0 2680.0 2595.0 2510.0 2425.0 2340.0 2255.0 2170.0 2085.0 2000.0 1915.0 1830.0 1745.0 1660.0 1575.0 1490.0 1405.0 1320.0 1235.0 1150.0 1065.0 980.0 895.0 810.0 725.0 640.0 555.0 470.0 385.0 895.0 215.0 130.0 45.0 -40.0 -125.0 -210.0 -295.0 -380.0 -465.0 -550.0 -635.0 -720.0 Y 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 Pad No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Symbol SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X -805.0 -890.0 -975.0 -1060.0 -1145.0 -1230.0 -1315.0 -1400.0 -1485.0 -1570.0 -1655.0 -1740.0 -1825.0 -1910.0 -1995.0 -2080.0 -2165.0 -2250.0 -2335.0 -2420.0 -2505.0 -2590.0 -2675.0 -2765.0 -2860.0 -2955.0 -3050.0 -3145.0 -3240.0 -3335.0 -3430.0 -3525.0 -3620.0 -3715.0 -3810.0 -3905.0 -4000.0 -4095.0 Y 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 742.5 Note: For PCB layout, the IC substrate must be connected to VSS or floating. Refer to the relationship between Duty Ratio and Common Output (Section 7.3.2). Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 5 EPL43102 43 Com / 102 Seg LCD Driver 5 Block Diagram SEG0 V0 V1 V2 V3 V4 VSS Voltage Followers LA TCHCIRCUIT SHIFT REGISTER SEG101 COM 0 COM COM 41 I SEGMENT DRIVER CIRCUITS COMMONDRIVER CIRCUITS VOUT Connect the capacitor Voltage Converter DISPLA DA RA Y TA M CO NA LUM DDRESS DECO DER INITIAL DISPLAY LINE REGISTER VR Voltage Regulator PAGE ADDRESS REGISTER LOW ADDRESS DECODER LINE COUNTER LINE ADDRESS DECODE FR CO NA LUM DDRESS CO UNTER Display Tim ing Generator Circuit CL /DOF FRS M /S CO NA LUM DDRESS REG ISTER INSTRUCTIO N DECODER Oscillator Bus holder INSTRUCTIO N REG ISTER STA TUS REG ISTER CLS OSC MPUInterface I/OBuffer ( Serial / Parallel ) IRS /CS1CS2A0 /RD/W RC86P/S /RES D7 D6 D5 D4 D3 D2 D1 D0 (E) (R/W) (SDI)(SCK)(SDO) Figure 5-1 System Block Diagram 6* Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 6 Pin Description 6.1 Power Supply Name VDD VSS I/O Power Power Description VDD Power Supply 0V (GND) LCD driver supply voltages. The voltage applied is determined by the LCD pixel and is changed by changing the impedance using an operational amplifier (OPA) for various applications. Voltage levels are determined based on V0, and must maintain the relative magnitudes shown below: V0V1V2V3V4Vss When the internal power circuit is active, these voltages are generated according to the state of the LCD bias. The selection of voltages is determined by the "LCD bias select" instruction, as shown in the table below. LCD Bias 1/8 Bias 1/7.5 Bias 1/7 Bias 1/6.5 Bias 1/6 Bias 1/5.5 Bias 1/5 Bias 1/4.5 Bias 1/4 Bias 1/3.5 Bias 1/3 Bias V0 V1 V2 V3 V4 Power V1 (7/8) x V0 (6.5/7.5) x V0 (6/7) x V0 (5.5/6.5) x V0 (5/6) x V0 (4.5/5.5) x V0 (4/5) x V0 (3.5/4.5) x V0 (3/4) x V0 (2.5/3.5) x V0 (2/3) x V0 V2 (6/8) x V0 (5.5/7.5) x V0 (5/7) x V0 (4.5/6.5) x V0 (4/6) x V0 (3.5/5.5) x V0 (3/5) x V0 (2.5/4.5) x V0 (2/4) x V0 (1.5/3.5) x V0 (1/3) x V0 V3 (2/8) x V0 (2/7.5) x V0 (2/7) x V0 (2/6.5) x V0 (2/6) x V0 (2/5.5) x V0 (2/5) x V0 (2/4.5) x V0 (2/4) x V0 (2/3.5) x V0 (2/3) x V0 V4 (1/8) x V0 (1/7.5) x V0 (1/7) x V0 (1/6.5) x V0 (1/6) x V0 (1/5.5) x V0 (1/5) x V0 (1/4.5) x V0 (1/4) x V0 (1/3.5) x V0 (1/3) x V0 6.2 LCD Driver Supply Name C1+ C1C2+ C2C3 C4 VOUT VR I/O O O O I/O I Description Boosted capacitor connecting terminals used for voltage booster. Boosted capacitor connecting terminals used for voltage booster. Boosted capacitor connecting terminals used for voltage booster. Voltage converter output V0 voltage adjustment pin Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 7 EPL43102 43 Com / 102 Seg LCD Driver 6.3 System Control Name I/O Description Master/slave operation select pin. - MS = "H": Master operation - MS = "L": Slave operation M/S CLS OSC. Power supply Circuit CL FR FRS /DOF M/S I "H" "L" "H" "L" * Available Unavailable Unavailable Available Available Unavailable O O I O O I O O Hi-Z O O I Note: * : Don't Care O : Output I : Input P/S I FR I/O C68 I /DOF I/O Select Interface mode of the MPU. When PS = "High": Parallel interface mode When PS = "Low": Serial interface mode LCD AC signal input/output pin. When used in master/slave mode (multi-chip), the FR pins must be connected to each other. - MS = "H": Output - MS = "L": Input Select the kind of the MPU to interface. When C68 = "High": 68-series MPU interface mode When C68 = "Low": 80-series MPU interface LCD Display blanking control pin. In multi-chip mode, the /DOF pin must be connected to each other. M/S = "H" (Master) : /DOF is output pin. Display "On" = "H", Display "Off" = "L" M/S = "L" (Slave) : /DOF is input pin. Via external control. Refer to the following table. Instruction /DOF H L Display "On" Display "Off" On Off Off Off CLS I Internal oscillator circuit enable / disable select pin. CLS = "H": Enable Internal oscillator circuit CLS = "L": Disable Internal oscillator circuit is (External display clock input to OSC pin) Display clock input/output pin. When the EPL43102 is used in master/slave mode (multi-chip), the CL pins must be connected to each other. CL I/O M/S "H" "L" CL Output Input 8* Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Name OSC FRS I/O I O IRS I TEST I Description When using an external oscillator, input the clock to the OSC pin. When using an internal oscillator, leave this pin open. Static driver output pin. This pin is used in combination with the FR pin. Internal resistor select pin. This pin selects the resistors for adjusting V0 voltage level and is available only in master mode. - IRS = "H": The internal resistors are used. - IRS = "L": The external resistors are used. V0 voltage is controlled using the external divider resistor connect the VR pin. Test pin. Fixed at VSS. 6.4 MPU Interface Name /RES I/O I Description Hardware reset input. The LSI is reset when this signal is pulled low. (Active low) These are the chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and also CS2 is "H" and allows the input/output of data or commands. /CS1 CS2 Status /CS1, CS2 I "L" "L" "H" "H" "L" "H" "L" "H" The device is not active. (D7~D0 is Hi-Z) Data and instruction are available. The device is not active. (D7~D0 is Hi-Z) The device is not active. (D7~D0 is Hi-Z) A0 I /WR (R/W) I /RD (E) I D0 to D7 I/O Used as register selection input. When A0 = "High", Data register When A0 = "Low", Instruction register When C68 = "High" (68-series MPU interfacing), used as Read (/WR = "High"), Write (/WR = "Low") When C68 = "Low " (80-series MPU interfacing), used as write enable input (/WR). When C68 = "High" (68-series MPU interfacing), used as read/write enable input (E). When C68 = "Low " (80-series MPU interfacing), used as read enable input (/RD). When serial mode, D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin and the others are not used. When parallel mode, D0 to D7 are used as bidirectional data bus pin. Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 9 EPL43102 43 Com / 102 Seg LCD Driver 6.5 LCD Driver Output Name I/O Description The LCD common output pins. Scan Data FR COMs Output Voltage COM0 to COM41 O H H L H L L Power Save Mode Vss V0 V1 V4 Vss COMI O These are two icon display pins. Both pins output the same signal. Leave these pins open when they are not used. The LCD segment output pins. Display Data FR SEGs Output Voltage Normal Display Reverse Display SEG0 to SEG101 O H L L H L Power Save Mode H V0 Vss V2 V3 Vss V2 V3 V0 Vss Refer to the Section 7.3.2 on the relationship between Duty Ratio and Common Output. 10 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 7 Function Description 7.1 System Interface Instruction Decoder Bus Holder Instruction Register Status Register MPU Interface I/O Buffer ( Serial/Parallel ) D7 D6 D5 D4 D3 D2 /CS1 CS2 A0 /RD /WR C86 P/S /RES (E) (R/W) (SDI)(SCK)(SDO) D1 D0 BUSY Figure 7-1 System Interface 7.2 MPU Interface 7.2.1 Chip Select The EPL43102 has two chip select pins /CS1 and CS2. When /CS1="L" and CS2="H", MPU interface is available. When the chip select pin is inactive (other /CS1 and CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or /WR inputs are not effective. If serial interface is selected, the shift register and counter are both reset. However, reset is always operated in any conditions of /CS1 and CS2. P/S Serial Mode (L) C68 SPI interface ( - ) 80-series (L) 68-series (H) A0 A0 A0 A0 /WR R/W /WR R/W /RD - /RD E D0~D4 * D5 SDO D6 SCK D7 SDI Parallel mode (H) Note: " D0~D7 D0~D7 * " Don't care ("High", "Low" or "Open") "-" Indicates that it is fixed to either "High" (VDD) or "Low" (VSS) Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 11 EPL43102 43 Com / 102 Seg LCD Driver 7.2.2 Selecting the Interface Type The EPL43102 can be operated with serial interface (SPI) and parallel interface (80series or 68-series) as selected by the P/S pin. 7.2.2.1 Serial Interface (SPI) When serial mode (PS = "L"), D6 (SCK) is used as serial clock input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data output pin. When the LSI is active (/CS1="L", CS2="H"), serial data input (D7), serial clock input (D6) and serial data output (D5) are enabled. The 8-bit shift register and 3-bit counter are reset to the initial condition when the chip is not selected. The data input/output from SDI/SDO terminal is MSB first as in the order of D7, D6...D0, and is latched at the rising edge of the serial clock SCK. Serial input data is display data when A0="H" and instruction when A0="L". The A0 input is read and identified at the rising edge of the (8 x n) serial clock pulse. Since the clock signal (D6) is easy to be affected by the external noise caused by the line length, operation check on the actual machine is recommended. /C 1 S C S2 SK C (D 6) SD I (D 7) SO D (D 5) A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 Figure 7-2 Serial Interface Signal Chart A0 0 0 1 1 /WR (R/W) 0 1 0 1 D7 (SDI) Instruction Write Invalid Display Data Write Invalid D5 (SDO) Status Read Status Read Status Read Display Data Read 12 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 7.2.2.2 Parallel Interface (8-bit Length) When the parallel input is selected (PS = "H"), D0~D7 can be connected directly to the 80-series or 68-series MPU by setting the C86 pin to high or low. A0 /RD /WR D7~D0 N D(N) D(N+1) D(N+2) D(N+3) D(N+4) Writing Timing A0 /RD /WR D7~D0 N Dummy D(N) D(N+1) D(N+2) D(N+3) Reading Timing Figure 7-3 Write and Read Timing Diagrams Common A0 H H L L L H L H 80-series /RD /WR H L H L 68-series R/W H L H L Description Display data read Display data write Register status read Write to the Instruction register 7.3 Data Transfer The EPL43102 uses a bus holder and an internal data bus for data transfer with MPU. When writing data from the MPU to the DDRAM, data is automatically transferred from the bus holder to the DDRAM. When reading data from the DDRAM to the MPU, data for the initial read cycle is stored in the bus holder (dummy read) and MPU reads this stored data from the bus holder for the next data read cycle. Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 13 EPL43102 43 Com / 102 Seg LCD Driver 7.3.1 Display Data RAM Page Address Register Line Address Decoder Low Address Decoder Initial Display Line Line Counter D is p la y D a ta R A M C o lu m n A d d re s s D e c o d e r C o lu m n A d d r e s s C o u n t e r C o l u m n A d d r e s s R e g is t e r Figure 7-4 Display Data RAM Diagram The display data RAM (DDRAM) stores pixel data for the LCD. It is a 43-row x 102column addressable array. It is possible to access any required bit by specifying the page address and the column address. The 43 rows are divided into 5 pages of 8 lines, 1 page with 2 lines (D0, D1) and the seventh page with a single line (D0 only). Each bit in the Display Data RAM corresponds to the each pixel of the LCD panel and controls the display by applying the following bit data. When in Normal Display : On = "1" , Off = "0" When in Inverse Display : On = "0" , Off = "1" Refer to Section 8.1.3, "Inverse Display On/Off" instruction for more details. 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 Normal Display Inverse Display Display Data RAM Figure 7-5 Display Data RAM, Normal and Inverse Liquid Crystal Display Diagrams The microprocessor (MPU) can read from and write to the RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into the RAM at the same time as data is being displayed without causing the LCD to flicker. 14 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) Register EPL43102 43 Com / 102 Seg LCD Driver Page Address P3,P2,P1,P0 Line Data Column Address Address (HEX) Common Output Output (1/42,1/43) (1/36,1/37) (1/32,1/33) (1/16,1/17) Common Output Common Output Common 0 0 0 0 D0 D1 D2 D3 D4 D5 D6 D7 PAGE0 00 01 02 03 04 05 06 07 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 0 0 0 1 D0 D1 D2 D3 D4 D5 D6 D7 PAGE1 08 09 0A 0B 0C 0D 0E 0F 0 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 PAGE2 10 11 12 13 14 15 16 17 0 0 1 1 D0 D1 D2 D3 D4 D5 D6 D7 PAGE3 18 19 1A 1B 1C 1D 1E 1F 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7 PAGE4 20 21 22 23 24 25 26 27 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 15 EPL43102 43 Com / 102 Seg LCD Driver Page Address P3,P2,P1,P0 Line Data Column Address Address (HEX) Common Output Output (1/42,1/43) (1/36,1/37) (1/32,1/33) (1/16,1/17) Common Output Common Output Common 0 1 0 1 D0 D1 D0 0 0 6 5 S E G 0 0 1 6 4 S E G 1 0 2 6 3 S E G 2 PAGE5 PAGE6 ----------------6 2 0 3 S E G 9 8 6 3 0 2 S E G 9 9 6 4 0 1 S E G 1 0 0 6 5 0 0 S E G 1 0 1 28 29 COM40 COM41 COMI COMI COMI COMI 0 1 1 0 ADC =0 Column Address (HEX) ADC =1 LCD Output --------- 7.3.2 Programmable Duty Ratio The duty ratio is selected by using the "Set Duty Ratio" instruction. The common output circuits are shown in the following figure. They are separated into three shift registers and controlled by the "duty ratio register". COM0 COM20 COM21 COM41 COMI Common Driver (21) Common Driver (21) Common Driver (1) 21-bit Shift Register 21-bit Shift Register 1-bit Shift Register 4 Duty Ratio Register Figure 7-6 Common Output Circuits 16 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Duty SHL COM0 ~ 3 1/9 1/8 1/17 1/16 1/25 1/24 1/33 1/32 1/37 1/36 1/43 1/42 0 1 0 1 0 1 0 1 0 1 0 1 Common Output Pins (COMxx, refer to the Pad No.) ~ 7 ~ 11 ~ 15 ~ 17 ~ 24 ~ 26 ~ 30 ~ 34 ~ COM38 ~ 41 COMI CCOM[4..7] CCOM[3..0] CCOM[8..15] CCOM[7..0] CCOM[12..23] CCOM[11..0] CCOM[16..31] CCOM[15..0] CCOM[18..35] CCOM[17..0] CCOM[0..41] CCOM[41..0] Relationship between Duty Ratio and Common Output COMI - COMI - COMI - COMI - COMI - COMI - CCOM[0..3] CCOM[7..4] CCOM[0..7] CCOM[15..8] CCOM[0..11] CCOM[23..12] CCOM[0..15] CCOM[31..16] CCOM[0..17] CCOM[35..18] Line address Initial Display Line Register The initial display line register assigns a DDRAM line address which corresponds to COM0 by using the "Initial display line set" instruction. It is used not only for normal display but also for vertical display scrolling and page switching without changing the contents of the DDRAM. However, the 43rd address for icon display cannot be assigned for the initial display line address. Line Counter The line counter provides a DDRAM line address. It initializes its contents at the switching of the frame reversal signal (FR), and also counts-up in synchronization with common timing signal. Column Address Counter The column address counter is an 8-bit preset counter which provides a DDRAM column address, and is independent of the page address register. It will increment (+1) the column address whenever "display data read" or "display data write" instructions are issued. However, the incrementing of the column address is stopped at column address 65H. The count-lock will be released by the "column address set" instruction again. The counter can invert the correspondence between the column address and segment driver direction by means of "ADC select" instruction. Page Address Register The page address register provides a DDRAM page address. Page Address 6 is used for icon display, and only D0 is valid. Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 17 EPL43102 43 Com / 102 Seg LCD Driver 7.4 LCD Driver Circuits COM0 COM41 COMI SEG0 SEG101 V0 V1 V2 V3 V4 VSS Common Driver Circuits Segment Driver Circuits Shift Register Display Timing Generator Circuit Latch Circuit From the Display Data RAM Figure 7-7 LCD Driver Circuits This driver circuit is configured by 42-common drivers, 102-segment drivers and 1icon-common driver. This LCD panel driver voltage depends on the combination of display data and FR (internal) signal. 7.4.1 Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. "Display on/off", "Inverse display on/off" and "Entire display on/off" instructions control only the contents of this latch circuit, they cannot change the contents of the DDRAM. 7.4.2 Shift Register Circuit The circuit contains a 42-bit shift register to shift and turn-on data required for the LCD drive common signals and 1-bit shift register used for icon. The clock of this shift register is generated by the display clock CL. 18 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Examples of 1/33 and 1/43 Duty (ICON enable) Driving Waveform 1/33 Duty 1/43 Duty 0 0 1 1 2 2 3 3 32 0 42 0 1 1 2 2 31 32 0 41 42 0 1 1 CL FR COM0 COM1 COM31 (COM41) COMI Figure 7-8 1/33 and 1/43 Duty Driving Waveform Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 19 EPL43102 43 Com / 102 Seg LCD Driver Examples of 1/32 and 1/42 duty (ICON disable) Driving Waveform 1/32 Duty 1/42 Duty 0 0 1 1 2 2 3 3 31 0 41 0 1 1 2 2 30 31 0 40 41 0 1 1 CL FR COM0 COM1 COM30 (COM40) COM30 (COM41) Figure 7-9 1/32 and 1/42 Duty Driving Waveform 20 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 7.4.3 Common Driver Circuit The Common driver circuit consists of 43 drive circuits. One of the four LCD driving level is selected by the combination of FR and data from the shift register. V0 VCON VSS Shift Data COM0~41,COMI V4 VCOFF Scan Data H L FR COMs Output Voltage V1 H L H L VSS V0 V1 V4 VSS FR Power save mode Figure 7-10 Common Driver Circuit 7.4.4 Segment Driver Circuit The Segment driver circuit consists of 102 driver circuits. One of the four LCD driving level is selected by the combination of FR and the display data transferred from the latch circuit. VSS VSON Display Data SEG0~101 FR V0 Display Data SEGs Output Voltage Normal Inverse Display Display V0 VSS V2 V3 VSS V2 V3 V0 VSS V3 VSOFF H H L H L V2 L Power save mode FR Figure 7-11 Common Driver Circuit Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 21 EPL43102 43 Com / 102 Seg LCD Driver 7.4.5 LCD Driving Waveform The following illustration is an example of how the common and segment drivers are attached to an LCD panel. CL SEG0 COM0 COM1 FR V0 V1 COM0 V4 VSS V0 V1 COM1 V4 VSS V0 V2 SEG0 V3 VSS V0 SEG0-COM0 -V0 Figure 7-12 LCD Driver Waveform 22 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 7.5 Internal Power Circuits LCD Driving Voltage Supply Voltage Followers VR Voltage Regulator IRS VOUT Connect the capacitor Voltage Converter Internal Power Circuits Figure 7-13 Internal Power Circuits The internal power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. There are voltage converter (V/C) circuits, voltage regulator (V/R) circuits, and voltage follower (V/F) circuits. They are valid only in master operation and controlled by "Power Control" instruction. For details, refer to Section 8, "Instruction Description". User Setup Only the internal power supply circuits are used Only the voltage Regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power Control V/C V/R V/F (VC VR VF) Circuits Circuits Circuits 111 On On On VOUT Open V0 Open V1~V4 Open 011 Off On On External input Open Open 001 Off Off On Open External Input Open 000 Off Off Off Open External External Input Input Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 23 EPL43102 43 Com / 102 Seg LCD Driver 7.5.1 Voltage Converter Circuits These circuits boost up the electric potential between VDD and VSS to 2, 3, 4, or 5 times towards the positive side and the boosted voltage is outputted from the VOUT pin. The boosting magnitude of the internal booster circuit is selected by the capacitor connection (Refer to the Figure below). The internal oscillator is required to be operating when using this converter, since the divided signal provided from the oscillator is used for the internal timing of this circuit. C1+ C1OPEN OPEN OPEN C3 C4 C2C2+ VOUT OPEN C1+ C1C3 C4 C2C2+ VOUT C1+ C1C3 C4 C2C2+ VOUT C1+ C1C3 C4 C2C2+ VOUT 2X 3X 4X 5X Boost Capacitors = 1 uF~4.7 uF Figure 7-14 Capacitor Connections 7.5.2 Voltage Regulator Circuits The voltage regulator determines the LCD driving voltage V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Since VOUT is the operating voltage of the operational-amplifier circuits, it is necessary to be applied internally or externally. For Equation 1, we determine V0 by Ra, Rb and VEV. Ra and Rb are connected internally or externally by the IRS pin. VEV which is the voltage of the electronic volume is determined by Equation 2, where the parameter is the value selected by instruction, "Set Contrast Control Mode", within the range 0 to 63. VREF, a constant voltage source is about 2V at TA=25C. 24 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver VOUT V0 Rb VEV (Constant reference voltage + electronic volume) VR Ra VSS Figure 7-15 Resistor Connection V 0 = (1 + Rb ) x VEV .....................Equation 1 Ra VEV = (1 - Register Value (R2 R1 R0) 000 001 010 011 100 101 110 111 (63 - ) ) x VREF ..........Equation 2 252 1+ (Rb/Ra) 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Value Small . . . . . . Large Refer to Section 8.20, "Regulator Resistor Select" instruction for further details. 0 1 .. .. 62 63 D5 0 0 . . 1 1 D4 0 0 . . 1 1 D3 0 0 . . 1 1 D2 0 0 . . 1 1 D1 0 0 . . 1 1 D0 0 1 . . 0 1 Refer to Section 8.91, "Set Contrast Control Mode" instruction for further details. Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 25 EPL43102 43 Com / 102 Seg LCD Driver Using Internal Resistors, Ra and Rb (IRS = "H") When the IRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. V0 is determined by using the two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Using External Resistors, Ra and Rb (IRS = "L") When IRS pin is "L", it is necessary to connect the external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a 1/43 duty ratio, the optimum operating voltage of the liquid can be calculated as: VLCD = 1 + 43 1 2 x 1 - 43 x Vth = 5.805 x Vth where Vth is the threshold voltage of the liquid crystal material used. 7.5.3 Voltage Follower Circuits FROM VOLTAGE REGULATOR V0 V1 0.890xV0 V2 0.880xV0 Total Req = 4M Switching Network 0.120xV0 0.110xV0 V3 V4 BYPASS CAPACITOR = 0.47uF~1uF OP TYPE VOLTAGE FOLLOWER Figure 7-16 OTP Voltage Follower Circuit The VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and those output impedance are converted by the voltage follower (OPA) to increase the drive capability. A total of six levels LCD reference voltage (V0, V1, V2, V3, V4, VSS) is generated by the voltage follower circuits. 26 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver LCD Bias 1/8 1/7.5 1/7 1/6.5 1/6 1/5.5 1/5 1/4.5 1/4 1/3.5 1/3 V1 0.875*V0 0.865*V0 0.855*V0 0.845*V0 0.835*V0 0.820*V0 0.800*V0 0.780*V0 0.750*V0 0.715*V0 0.665*V0 V2 0.750*V0 0.735*V0 0.715*V0 0.690*V0 0.665*V0 0.635*V0 0.600*V0 0.555*V0 0.500*V0 0.430*V0 0.335*V0 V3 0.250*V0 0.265*V0 0.285*V0 0.310*V0 0.335*V0 0.365*V0 0.400*V0 0.445*V0 0.500*V0 0.570*V0 0.665*V0 V4 0.125*V0 0.135*V0 0.145*V0 0.155*V0 0.165*V0 0.180*V0 0.200*V0 0.220*V0 0.250*V0 0.285*V0 0.335*V0 Different duty radio requires different bias level. For optimum bias level, BL can be calculated from: BL = 1 Duty ratio + 1 Changing the bias system from the optimum will have a consequence on the contrast and viewing angle. The LCD Bias affects the display quality. But for the purpose of reducing the current consumption, the unsuitable bias may be selected. Hence, the LCD Bias could be selected by "Select LCD bias" instruction. 7.6 LCD Display Circuits FR Display Timing Generator Circuit CL /DOF FRS M/S CLS Oscillator OSC Figure 7-17 LCD Display Circuit Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 27 EPL43102 43 Com / 102 Seg LCD Driver 7.6.1 Oscillator The on-chip RC type oscillator provides the display clock and voltage converter timing clock. It has low power consumption and its frequency is nearly independent of VDD. When "M/S="H" and "CLS"="H", the oscillator circuit is enabled. When CLS="L", the oscillator is stopped, and the oscillator clock has to be input to the OSC pin. The oscillator circuit is available in master mode only. The oscillator signal is divided and output as display clock at CL pin. RC Oscillator To internal circuit CLS OSC Sleep mode Figure 7-18 RC Oscillator 7.6.2 /DOF Pin Description The pin is used to control the blinking of the LCD display. Instruction Display "ON" Display "OFF" M/S= "H" /DOF (Output) "H" "L" LCD On LCD Off M/S="L" /DOF (Input) ="H" /DOF (Input) ="L" LCD Off LCD Off When the "Power Save" Instruction is activated, the /DOF pin is set to low level. 7.6.3 Display Timing Generator Circuit This circuit generates some signals to be used to display the LCD. When used in master/slave mode (multi-chip), some pins must be connected to each other. That is due to synchronization output. The display clock (CL) generated by the oscillation clock, generates a clock for the line counter and a latch signal for the display data latch. The line address of the on-chip RAM is generated in synchronization with the display clock (CL). While the 102-bit display data is latched by the display data latch circuit in synchronization with the display clock, the display data which is read to the LCD driver is completely independent from any access to the display data RAM from the microprocessor. 28 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver The display clock generates an LCD frame reversal signal (FR) which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. When this EPL43102 is used for a multi-chip, the slave chip must receive the FR, CL, /DOF signals from the master. Operation Mode Master (M/S="H") Slave (M/S="L") Internal oscillator is enable(CLS="H") Internal oscillator is disable (CLS="L") Internal oscillator is disable (CLS ="L" or "H") FR CL /DOF FRS OSC Output Output Output Output Open Output Output Output Output Input Input Input Input Input Input Input Hi-Z Hi-Z Open Open Note: Open means leave this pin open 7.6.4 Oscillator Frequency The EPL43102 contains an RC oscillator. The frame frequency (fFM) is derived from the RC circuit's oscillation frequency (fOSC) by giving it an appropriate value. The relationship between the oscillation frequency (fOSC), display clock frequency (fCL) and the frame frequency (fFM) is shown in an equation below. The fOSC could be selected from an internal or external oscillator via the CLS pin, the fCL could be selected using the "Set display clock CL frequency" instruction, and frame frequency could be calculated using the following equation. fCL = (Duty ratio) x (Frame frequency) 7.7 Reset Circuit When the /RES input comes to the "L" level, these LSI return to their default state. Their default states are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Display OFF Normal display ADC select: Normal (ADC select instruction D0 = "L") SHL select: Normal (SHL select instruction D3 = "L") Power control register: (D2, D1, D0) = (0, 0, 0) Serial interface internal register data clear Duty ratio = 1/43 CL frequency Register (D4, D3, D2, D1,D0) = (0, 0, 0, 0, 1, 1) LCD power supply bias level = (1/8) Entire display OFF (Entire display instruction D0 = "L") Power saving clear 29 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 12. 13. Modify-Read OFF Static indicator OFF Static indicator register: (D1, D2) = (0, 0) 14. 15. 16. 17. 18. Display initial line set to the first line: 0 Column address set to Address: 0 Page address set to Page: 0 V0 voltage regulator internal resistor ratio set mode clear: (R2, R1, R0) = (0, 0, 0) Contrast control set mode clear Contrast control register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0) 8 Instruction Description Instruction A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Read Data Write Data Status 0 0 0 0 0 0 0 0 1 0 0 * * * ICON D2 D1 D0 0 * 0 * 0 1 0 * 0 0 0 0 * 0 * 1 0 D4 0 * 0 0 D3 0 D3 1 D3 0 D3 0 1 0 Description Read data from DDRAM Write data into DDRAM Read the internal status Set duty ratio Mode Select the duty ratio Set CL frequency Mode Set CL frequency Register Set LCD Bias select Mode Select the LCD Bias Read Display Data Write Display Data Read Status Set Duty Ratio Mode Duty Ratio Register Set CL frequency Mode CL frequency Register Set LCD Bias select Mode LCD Bias select Register Display On/Off Initial Display Line Set Contrast Control Mode Set Contrast Control Register Set Page Address Set Column Address MSB Set Column Address LSB 1 * 1 * 1 * 1 0 1 * 1 0 0 D2 D1 D0 1 0 1 D2 D1 D0 1 D5 D4 0 0 Turn on/off LCD panel 1 Don When DON=0: display off When DON=1: display on D2 D1 D0 Specify DDRAM line for COM0 0 0 1 Set Contrast Control Mode Set Contrast Control Register D5 D4 1 0 0 1 1 0 D2 D1 D0 Page Address Higher order Column Add. Lower order column Add. ADC Select 0 1 0 1 0 1 0 0 0 0 Inverse Display ON/OFF 30 * 0 1 0 1 0 1 0 0 1 1 Set page address DDRAM column address of the Higher 4 bits DDRAM column address of the lower 4 bits Select segment direction When ADC=0: normal direction ADC (SEG0 SEG101) When ADC=1: reverse direction (SEG101 SEG0) Select normal/inverse display REV 0: Normal display 1: Inverse display on Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Instruction Entire Display ON/OFF Set Modify-read Reset Modify-read Reset A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 Description Select normal/entire display ON EON When EON=0: normal display. SHL Select 0 1 0 1 1 0 0 Power Control Regulator Resistor Select Set Static Indicator Mode Set Static Indicator Register Power Save Note: * Don't care 0 0 0 0 - 1 0 1 1 - 0 0 0 0 - 0 0 1 * - 0 0 0 * - 1 1 1 * - 0 0 0 * - When EON=1: entire display ON Set modify-read mode Release modify-read mode Initialize the internal functions Select COM output direction When SHL=0: normal direction SHL * * * (COM0 COM41) When SHL=1: reverse direction (COM41 COM0) 1 VC VR VF Control power circuit operation Select internal resistance ratio of 0 R2 R1 R0 the regulator resistor Set static indicator mode 1 1 0 SM When SM = 0: off When SM = 1: on 0 0 0 * * S1 S0 Set static indicator register Compound instruction of display OFF and entire display ON 8.1 Read Display Data The 8-bit data from the display data RAM specified by the column address and page address can be read by this instruction. As the column address is automatically incremented by 1 after each instruction execution, the microprocessor can continuously read data from the addressed page. A0 1 /RD 0 /WR 1 D7 D6 D5 D4 D3 D2 D1 D0 Read Data 8.2 Write Display Data The 8-bit display data from the microprocessor can be written to the RAM location specified by the column address and page address. After writing the display data, the column address is automatically incremented so that the microprocessor can continuously write data to the addressed page. A0 1 /RD 1 /WR 0 D7 D6 D5 D4 D3 D2 D1 D0 Write Data Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 31 EPL43102 43 Com / 102 Seg LCD Driver 8.3 Read Status This instruction reads out the internal status of the "ADC select", "Display on/off" and "Reset". A0 0 /RD 0 /WR 1 D7 D6 ADC D5 D4 D3 0 D2 0 D1 0 D0 0 On/Off RESET Flag Description It shows the correspondence between the column address and segment drivers. ADC = 0 : Reverse direction (SEG101 SEG0) ADC = 1 : Normal direction (SEG0 SEG101) This bit indicates the ON/OFF state of the display. 0: Display ON 1: Display OFF Indicates the initialization in progress by RESETB signal. RESET = 0 : Normal display operation state RESET = 1 : Internal reset operation state with reset command. ADC On/Off RESET 8.4 Set Duty Ratio (Two-Byte Instruction) This consists of 2-byte instruction. The first instruction sets the duty ratio mode, the second instruction updates the contents of the duty ratio register. After the second instruction, the set duty mode is released. The LSI cannot accept any instructions except for the "Set duty ratio register" during the set duty ratio mode. 8.4.1 Set Duty Ratio Mode (First Instruction) A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 8.4.2 Set Duty Ratio Register (Second Instruction) A0 0 /RD /WR 1 0 D7 * D6 * D5 * D4 * D3 ICON D2 0 0 0 0 1 1 D1 0 0 1 1 0 0 D0 0 1 0 1 0 1 Duty Ratio 8 (+ICON) 16 (+ICON) 24 (+ICON) 32 (+ICON) 36 (+ICON) 42 (+ICON) ICON : "0" Disable COMI (icon display) pin ICON : "1" Enable COMI (icon display) pin 32 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 8.5 Set Display Clock CL Frequency (Two-Byte Instruction) The display clock CL affects the current consumption and the frame frequency affects the flicker, so fine adjustments are required for the display clock CL and the frame frequency. 8.5.1 Set CL Frequency Select Mode (First Instruction) A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0 8.5.2 Set CL Frequency Select Register (Second Instruction) A0 0 /RD /WR 1 0 D7 * D6 * D5 * D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 * D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 * D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * CL Frquency fOSC fOSC / 2 fOSC / 3 fOSC / 4 fOSC / 5 fOSC / 6 fOSC / 7 fOSC / 8 fOSC / 9 fOSC / 10 fOSC / 11 fOSC / 12 fOSC / 13 fOSC / 14 fOSC / 15 fOSC / 16 fOSC / 32 8.6 Select LCD Bias (Two-Byte Instruction) This instruction selects the LCD bias ratio of the voltage required for driving the LCD. 8.6.1 Set the LCD Bias Select Mode (First Instruction) A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 1 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 33 EPL43102 43 Com / 102 Seg LCD Driver 8.6.2 Set the LCD Bias Select Register (Second Instruction) A0 0 /RD /WR 1 0 D7 * D6 * D5 * D4 * D3 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 LCD Bias 1/3 1/3.5 1/4 1/4.5 1/5 1/5.5 1/6 1/6.5 1/7 1/7.5 1/8 8.7 Display On/Off This instruction is used to control the turning on or off of the LCD panel regardless of the contents of the DDRAM. A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Display On or Off 0 :Off 1 :On 8.8 Initial Display Line This instruction sets the line address of the display RAM to determine the initial display line. The initial display line corresponds to COM0. The display area read from the display data RAM corresponds to the number of lines set by the Duty select command. A0 0 /RD /WR 1 0 D7 0 D6 1 D5 0 0 . . 1 1 D4 0 0 . . 0 0 D3 0 0 . . 1 1 D2 0 0 . . 0 0 D1 0 0 . . 0 0 D0 0 1 . . 0 1 Line Address for COM0 0 1 . . 40 41 8.9 Electronic Contrast Control Set (Two-Byte instruction) This consists of 2-byte instruction. The first instruction sets contrast control mode, the second instruction updates the contents of the contrast control register. After second instruction, the contrast control mode is released. The LSI cannot accept any instructions except for the "Set Contrast Control Register" during the Contrast Control Mode. 34 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 8.9.1 Set Contrast Control Mode (First Instruction) A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 8.9.2 Set Contrast Control Register (Second Instruction) A0 0 /RD /WR D7 1 0 * D6 * D5 0 0 . . 1 1 D4 0 0 . . 1 1 D3 0 0 . . 1 1 D2 0 0 . . 1 1 D1 0 0 . . 1 1 D0 0 1 . . 0 1 Electronic Volume Value () 0 Minimum 1 . . 62 63 8.10 Set Page Address This instruction sets the page address of the display data RAM from the microprocessor into the page address register. It is possible to access any required bit in the display data RAM by specifying the page address and the column address. Along with the column address, the page address defines the address of the display RAM used to write or read the display data. Changing the page address does not affect the display status. Page 8 is assigned for the icon display. Only D0 is valid. A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 1 D3 0 0 . . 0 D2 0 0 . . 1 D1 0 0 . . 1 D0 0 1 . . 0 Page Address 0 1 . . 6 8.11 Set Column Address This instruction sets the column address of the display data RAM from the microprocessor into the column address register. When accessing the display data RAM from the MPU, the column address is incremented. The incrementing of the column address is stopped at address 65H. A0 0 /RD /WR 1 0 D7 0 D6 0 D5 0 D4 1 0 A2 0 0 . . 1 1 D3 A7 A3 A1 0 0 . . 0 0 D2 A6 A2 D1 A5 A1 A0 0 1 . . 0 1 D0 A4 A0 Column Address Setting Upper 4-bit Lower 4-bit Column Address 0 1 . . 100 101 35 A7 0 0 . . 0 0 A6 0 0 . . 1 1 A5 0 0 . . 1 1 A4 0 0 . . 0 0 A3 0 0 . . 0 0 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 8.12 ADC Select This instruction selects the segment driver direction. Normal or reverse can be selected in the correlation between the display data RAM column address and the segment output terminal. A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 Segment Driver Direction Normal Reverse D0 = 0 Normal D0 = 1 Reverse Column addresses 00H to 65H correspond to segment outputs 0 to 101. Column addresses 00H to 65H correspond to segment outputs 101 to 0. 8.13 Inverse Display On/Off This instruction is used to invert the display status of the LCD panel without rewriting the contents of the display data RAM. A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 Display Status Normal Inverse D0 = 0 Normal D0 = 1 Inverse Display data "1" turns the LCD on. Display data "0" turns the LCD on. 8.14 Entire Display On/Off This instruction forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM will be retained. This instruction has priority over the Reverse Display On/Off instruction. A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 Entire Display On/Off Normal Entire display on 8.15 Set Modify-Read This instruction stops the automatic increment of the column address by the Read Display Data instruction, but the column address is still incremented by the Write Display Data instruction. This instruction can reduce the load of the MPU. During the display, the data in a specific DDRAM area is repeatedly changed for cursor blinking or other functions. This mode is canceled by the Reset Modify-read instruction. A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 36 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 8.16 Reset Modify-Read This instruction cancels the Modify-read mode. The column address of the display data RAM returns to the address before the Read Modify Write is executed. A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 8.17 Reset This instruction resets the initial display line, column address, page address, and the common output status is reset to their initial status, but does not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the /RES pin. A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Reset status by "Reset" instruction: 1. Read modify write off 2. Static indicator off and static indicator register: (S1, S0) = (0, 0) 3. Initial display line address: (00)H 4. Column address: (00)H 5. Page address: (0) page 6. SHL select: Normal mode (D3 = 0) 7. Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) 8. Sets contrast control set mode off and contrast control register: (20)H 8.18 SHL Select The COM output scanning direction is selected by this instruction which determines the LCD driver output status. A0 0 /RD /WR 1 0 D7 1 D6 1 D5 0 D4 0 D3 0 1 D2 * D1 * D0 * Common Driver Direction Normal Reverse Note: * Don't care D3 = 0 Normal D3 = 1 Reverse Normal direction (COM0 COM 41) Reverse direction (COM41 COM 0) Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 37 EPL43102 43 Com / 102 Seg LCD Driver 8.19 Power Control This instruction is used to select one of the eight power circuit functions by using the 3-bit register. An external power supply and part of the internal power supply functions can be used simultaneously. A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 VC D1 VR D0 VF VC: Voltage converter 0: Off 1: On VR: Voltage regulator VF: Voltage follower 8.20 Regulator Resistor Select This selects the resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit for more details. A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 R2 D1 R1 D0 R0 R2 0 0 .. 1 1 R1 0 0 .. 1 1 R0 0 1 .. 0 1 [Rb/Ra] Ratio Small ... .. .. Large 8.21 Set Status Indicator (Two-Byte Instruction) This consists of two bytes instruction. The first byte instruction (Set Static Indicator Mode) enables the second byte instruction (Set Static Indicator Register) to be valid. The first byte sets the static indicator on/off. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this status indicator state is released after setting the data of the indicator register. 8.21.1 Set Status Indicator Mode (First Instruction) A0 0 /RD /WR 1 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 1 Static Indicator Off On 38 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 8.21.2 Set Status Indicator Register (Second Instruction) A0 0 /RD /WR 1 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 0 0 1 1 D0 0 1 0 1 Off On (Blink at 4-frame intervals) On (Blink at 2-frame intervals) On (Turn on at all time) Status 8.22 Power Save (Compound Instruction) Static indicator OFF Static indicator ON Power saver (compound command) [ Display OFF ] [ Entire Display ON ] Static Indicator ON Sleep mode Standby mode Reset instruction Power Save OFF ( Compound Instruction ) [ Entire Display OFF ] [ Display ON ] [ Static Indicator ON ] Power Save OFF ( Compound Instruction ) [ Entire Display OFF ] [ Display ON ] Cancel Sleep mode Cancel Standby mode The current consumption can be greatly reduced by entering the power save status and by inputting the "Entire Display ON" instruction while the display is in OFF mode. According to the status in static indicator mode, power save is entered through one of two modes (sleep and standby mode). When Static Indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the "Display ON" & "Entire Display OFF" instruction. Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 39 EPL43102 43 Com / 102 Seg LCD Driver 8.22.1 Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are stopped. 2. All liquid crystal drive circuits are stopped, and the segment and common driver output VSS level. When a "static indicator on" instruction is issued in sleep mode, the LSI goes into a standby mode. 8.22.2 Standby Mode All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows: 1. The power supply circuit for LCD drive is stopped. The oscillator circuit will be operating. 2. The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level. The static display section will be operating. When a reset instruction is issued in the standby mode, the LSI goes into the sleep mode. 40 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 9 Application Information 9.1 Instruction Procedure Examples 9.1.1 Initial Setup (From power application to display ON using internal power supply circuits) V D D -V S S P o w e r O N Pow er s ta b iliz a tio n In p u t R e s e t S ig n a l W a it fo r m o r e th a n 2 0 m s In itia l s e ttin g s s ta te (d e fa u lt) U s e r s e ttin g s v ia in s tr u c tio n in p u t (1 ) D U T Y s e le c t L C D b ia s s e le c t C L fr e q u e n c y s e le c t A D C s e le c t S H L s e le c t U s e r s e ttin g s v ia c o m m a n d in p u t (2 ) R e g u la to r r e s is to r s e le c t C o n tr a s t c o n tr o l v o lu m e U s e r s e ttin g s v ia c o m m a n d in p u t (3 ) P o w e r c o n tro l V C ,V R ,V F = (1 ,1 ,1 ) W a itin g fo r m o r e th a n 3 0 0 m s to s ta b iliz e p o w e r le v e ls th e L C D E n d o f in itia l s e ttin g s L C D d is p la y s c r e e n s e ttin g s D is p la y s ta r t lin e s e t W r itin g s c r e e n d a ta , e tc . D is p la y O N Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 41 EPL43102 43 Com / 102 Seg LCD Driver "Modify-read" Sequence Set Page Address Set Column Address Set modify-read Dummy read Data read Data write NO Change complete YES End External Oscillator Input" Sequence Set CL frequency select mode Set CL frequency select register Input the clock to OSC pin End 42 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 9.2 Program Examples Use Elan RISC II MCU assembly ;***************************************************************************** ; Initialization Setting Example of EPL43102 ;***************************************************************************** INI_DRIVER_IC: MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL MOV CALL BS MOV CALL CALL MOV CALL CALL RET A,#LCD_COM_RESET WRITE_LCD_1BYTE A,#LCD_COM_DUTY WRITE_LCD_1BYTE A,#DUTY_SET WRITE_LCD_1BYTE A,#LCD_COM_BIAS WRITE_LCD_1BYTE A,BIAS_SET WRITE_LCD_1BYTE A,#LCD_COM_FREQ WRITE_LCD_1BYTE A,#CL_FREQ WRITE_LCD_1BYTE A,#LCD_ADC_SET WRITE_LCD_1BYTE A,#LCD_SHL_SET WRITE_LCD_1BYTE A,#LCD_REGULATOR_RES_SET WRITE_LCD_1BYTE A,#LCD_COM_CONTRAST WRITE_LCD_1BYTE A,#CONTRAST_SET WRITE_LCD_1BYTE A,#LCD_POWER_CONTROL_SET WRITE_LCD_1BYTE REG_CPUCON,F_CKS A,#150 WAIT_A_MS LCD_DISPLAY_ON A,#LCD_DISPLAY_INI_LINE WRITE_LCD_1BYTE LCD_DATA_WRITE ;WRITING SCREEN DATA ;TURN ON LCD ;SET INITIAL DISPLAY LINE ;ADD CLOCK BY OSC PIN (CLOCK FROM CPU) ;WAIT TO STABILIZE THE LCD POWER ;SET POWER CONTROL (INTERNAL OR EXTERNAL) ;SET CONTRAST 2ND INSTRUCTION ;SET CONTRAST 1ST INSTRUCTION ;SET REGULATOR RESISTOR 1+(Rb/Ra) ;SET SHL FUNCTION SELECT ;SET ADC FUNCTION SELECT ;SET CL FREQUENCE 2ND INSTRUCTION ;SET LCD CL FREQUENCY 1ST INSTRUCTION ;SET BIAS 2ND INSTRUCTION ;SET LCD BIAS 1ST INSTRUCTION ;SET DUTY 2ND INSTRUCTION ;SET DUTY 1ST INSTRUCTION ;INITIAL SETTINGS STATE (DEFAULT) Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 43 EPL43102 43 Com / 102 Seg LCD Driver ************************************************************************************* ; Write Display_Picture Data into Display Data RAM of EPL43102 ;************************************************************************************ DATA_WRITE: TBPTL TBPTM TBPTH #DISPLAY_PICTURE*2 #DISPLAY_PICTURE/0x80 #DISPLAY_PICTURE/0x8000 ;DEFINE DISPLAY PICTURE DATA INDEX DATA_WRITE_43102: MOV MOV DATA_W1: MOV MOV BC MOV ADD CALL MOV CALL MOV CALL BS DATA_W2: TBRD CALL DEC JBS DEC JBS BC RET 01,REG_ACC WRITE_LCD_1BYTE REG_LCDARL REG_STATUS,F_C,DATA_W2 REG_LCDARH REG_STATUS,F_C,DATA_W1 REG_PORTB,F_LCD_A0 ;LCD /A0 = 0 FOR INSTRUCTION OUTPUT ;IDENTIFY RES_STATUS CARRY BIT SET OR NOT ;ACCESS THE DATA OF DISPLAY_PICTURE A,#LINE_X_MAX REG_LCDARL,A REG_PORTB,F_LCD_A0 A,#LCD_COM_PAGE A,REG_LCDARH WRITE_LCD_1BYTE A,#0b00000000 WRITE_LCD_1BYTE A,#0b00010000 WRITE_LCD_1BYTE REG_PORTB,F_LCD_A0 ;SET LCD /A0 = 1 DATA OUTPUT ;SET HIGHER ORDER COLUMN ADDRESS=0000 ;SET LOWER ORDER COLUMN ADDRESS=0000 ;SET LCD /A0=0 INSTRUCTION OUTPUT ;SET MAX SEGMENTS OF DDRAM A,#LINE_Y_MAX REG_LCDARH,A ;MAX PAGES OF DDRAM 44 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver ;***************************************************************************** ; Write One Byte Data into DDRAM (Parallel Mode 80 Series) ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_1BYTE: JBS REG_DCRG,F_LAHEN,WRITE_LCD_1BYTE_1 BC REG_PORTC,F_LCD_WR ;CHECK REG_DCRG LAHEN BIT=1 OR NOT ;SET /WR=0 ENABLE WRITE ;MOVE A PORT_G ;Write low pulse( Wait 2 instruction cycles) MOV REG_DATA,A NOP NOP BS REG_PORTC,F_LCD_WR NOP NOP NOP NOP RET WRITE_LCD_1BYTE_1: MOV REG_DATA, RET ;SET /WR=1 DISABLE WRITE ;MOVE A PORT_G ;***************************************************************************** ; Read One Byte Data into DDRAM (Parallel Mode 80 Series) ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC NOP NOP MOV A,REG_DATA NOP BS NOP RET REG_PORTB,F_LCD_RD ;SET /RD=1 DISABLE READ ;MOVE PORT_G A REG_PORTB,F_LCD_RD ;SET /RD=0 ENABLE READ Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 45 EPL43102 43 Com / 102 Seg LCD Driver 10 Electrical Characteristics 10.1 Absolute Maximum Ratings Parameter Power supply voltage Driver supply voltage Input voltage Operating temperature range Storage temperature range Applicable Pins VDD VOUT All Input Symbol VDD VLCD VIN TA Condition Rated Value -0.3 to +7 -0.3 to +17 -0.3 to VDD+0.3 -30 to +80 C -55 to +125 V Unit 10.2 Recommended Operating Conditions Parameter Power supply Voltage Voltage converter output voltage Output voltage Applicable Pins VDD VOUT Input voltage Operating temperature range Rated Value Symbol Condition Min. VDD VOUT VOH VOL VIH VIL TA 2.2 4.0 0.7VDD VSS 0.7VDD VSS 0 Typ. Max. 5.5 15 VDD 0.3VDD VDD 0.3VDD 40 C V Unit 46 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 10.3 DC Characteristics VSS=0V, VDD=2.6 to 3.3V, TA= -30~80C Parameter Power supply voltage Voltage converter input voltage Applicable Pins VDD VDD VDD VDD VDD - V0 V0 V1 V2 V3 V4 1 Symbol VDD VDD2 VDD3 VDD4 VDD5 VREF0 VREF20 VREF40 V0 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT RON RRESET IOH IOL Condition - 2 x boost 3 x boost 4 x boost 5 x boost TA = 0C TA = 20C TA = 40C TA = 0~40C 2.2 Rated Value Min. Typ. 2.16 2.05 1.94 V0 V0 V1 V2 V3 V4 99 2 800 50 -4 2.2 Max. 5.5 5.5 5.0 3.75 3.0 2.25 2.14 2.02 V0+4% 100 5 1200 75 -5 3.2 1 3 Unit Reference voltage Regulated voltage OP Amp voltage output of LCD power supply Voltage converter output voltage LCD driver ON resistance Reset resistor Output current (Source and Drain) Input leakage current Output Tri-state Dynamic current consumption (1/43 duty) No load 2&3 2.2 2.2 2.2 2.2 2.07 1.96 1.86 V0-4% 95 400 25 -3 1.2 V mV VOUT COMn SEGn /RES 5 4 x2/x3/x4/x5 No load Current load Iload= 50A VDD=3V, Vin=0V VDD=3V, Vin=1.7V VDD=3V, VOH=2.4V VDD=3V, VOL=0.2V VIN= VDD or 0V VDD=3V, TA=25C, Five boosting, Internal OSC, fOSC=22kHz, 1/43 duty ratio, no load All display pattern off, VDD=3V, TA=25C Double boosting, External OSC,. fOSC=22kHz, 1/32 duty ratio, no load All display pattern off V0=3.6V, V1=2.4V (No load) VOH=2.8V V0=3.6V, V4=1.2V (No load) VOL=0.8V % k mA A All Input 5 IIL IDDD1 70 100 A Dynamic current consumption (1/32 duty) IDDD2 40 55 A V1 sink ability V1 Isv1 0.75 1 A V4 source ability V4 Isv4 -0.75 -1 A Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 47 EPL43102 43 Com / 102 Seg LCD Driver Parameter Current consumption Frame frequency Internal Oscillator frequency External input Oscillator Applicable Pins Symbol IDDs1 IDDs2 fFM Condition Standby mode Sleep mode - TA=25C TA=25C 17 Rated Value Min. Typ. 5 1 85 22 22 Max. 10 2 27 Unit A Hz kHz OSC fOSC fOSC Note 1 : V 0 = (1 + (63 - ) Rb ) x VEV ; VEV = (1 - ) x VREF Ra 252 2 : V1 (7/8) x V0 (6.5/7.5) x V0 (6/7) x V0 (5.5/6.5) x V0 (5/6) x V0 (4.5/5.5) x V0 (4/5) x V0 (3.5/4.5) x V0 (3/4) x V0 (2.5/3.5) x V0 (2/3) x V0 V2 (6/8) x V0 (5.5/7.5) x V0 (5/7) x V0 (4.5/6.5) x V0 (4/6) x V0 (3.5/5.5) x V0 (3/5) x V0 (2.5/4.5) x V0 (2/4) x V0 (1.5/3.5) x V0 (1/3) x V0 V3 (2/8) x V0 (2/7.5) x V0 (2/7) x V0 (2/6.5) x V0 (2/6) x V0 (2/5.5) x V0 (2/5) x V0 (2/4.5) x V0 (2/4) x V0 (2/3.5) x V0 (2/3) x V0 V4 (1/8) x V0 (1/7.5) x V0 (1/7) x V0 (1/6.5) x V0 (1/6) x V0 (1/5.5) x V0 (1/5) x V0 (1/4.5) x V0 (1/4) x V0 (1/3.5) x V0 (1/3) x V0 LCD Bias 1/8 Bias 1/7.5 Bias 1/7 Bias 1/6.5 Bias 1/6 Bias 1/5.5 Bias 1/5 Bias 1/4.5 Bias 1/4 Bias 1/3.5 Bias 1/3 Bias V0 3 : The target value of V0~V4 is Theoretical Value 50mV 4 5 : Input pin D0~D7, A0, /RD, /WR, /CS1, CS2, CLS, M/S, C86, P/S, IRS : Output pin D0~D7, FR, FRS, /DOF, CL 48 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 10.4 AC Characteristics Serial Interface Timing Characteristics /CS1, CS2 tCSS tCHS A0 /WR (R/W) tASS tCYCS tCLLS tDSS tCLHS tDHS tAHS D6 (SCK) D7 (SDI) tDDS tOHS D5 (SDO) VSS=0V, VDD=2.6 to 3.3V, TA= 0~40C Parameter Chip Select Setup Time Chip Select Hold Time Address Setup time Address Hold time Data Setup Time Data Hold Time Clock Cycle Time Clock L Time Clock H Time Data Delay Time Data Disable Time Applicable Pins /CS1 CS2 A0 R/W D7 (SDI) D6 (SCK) D5 (SDO) Symbol tCSS tCHS tASS tAHS tDSS tDHS tCYCS tCLLS tCLHS tDDS tOHS Condition Rated Value Min. 100 100 100 100 80 80 300 100 100 CL= 100 pF 10 Max. 80 50 ns Unit DATASCK SCKDATA Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 49 EPL43102 43 Com / 102 Seg LCD Driver 10.5 80-Family MPU Read/Write Timing Characteristics tAH8 A0 /CS1 (CS2) tAW8 tCC8 tCYC8 /WR,/RD tDS8 tDH8 D0 to D7 (Write) tACC8 tOH8 D0 to D7 (Read) VSS = 0V, VDD = 2.6 to 3.3V, TA = 0~40C Parameter Address Setup Time Address Hold Time System Cycle Time Pulse Width(/WR) Pulse Width(/RD) Data Setup Time Data Hold Time Read Access Time Output Disable Time Applicable Pins A0 A0 /WR /RD D0~D7 Symbol tAW8 tAH8 tCYC8 tCC8 tDS8 tDH8 tACC8 tOH8 Condition CL=100pF Rated Value Min. 0 0 500 160 200 20 10 10 Max. 60 40 ns Unit 50 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 10.6 68-Family MPU Read/Write Timing Characteristics tcyc6 E tAW6 tEW A0 R/W tAH6 /CS1 (CS2) tDS6 tDH6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) VSS=0V, VDD=2.6 to 3.3V, TA= 0~40C Parameter Address Setup Time Address Hold Time System Cycle Time Pulse Width(/WR) Pulse Width(/RD) Data Setup Time Data Hold Time Read Access Time Output Disable Time Applicable Pins A0 R/W A0 E Symbol tAW6 tAH6 tCYC6 tEW tDS6 tDH6 tACC6 tOH6 Condition CL=100pF Rated Value Min. 0 0 500 160 200 20 10 10 Max. 60 40 ns Unit D0~D7 Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 51 EPL43102 43 Com / 102 Seg LCD Driver 11 Pin Configuration Input Pin Configuration VDD Input/Output Pin Configuration Input/Output Pin Configuration VDD Output data Output enable Input enable 52 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver Output Pin Configuration VDD R e s e t I n p u t Reset Pin Configuration VDD Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 53 EPL43102 43 Com / 102 Seg LCD Driver LCD Output Pin Configuration V0 V0 V1 COMMON OUTPUT SEGMENT OUTPUT V2 V4 V3 VSS VSS 54 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 12 MPU Interface Elan 8-bit MPU ( with external memory ) VDD VCC PORT D_1 PORT A,B PORT D_4 PORT D_5 A0 /CS1 CS2 VCC C68 EPL43102 LCD PANEL RISC2 MPU PORT G PORT D_2 PORT D_3 /RES GND D0 ~D7 /RD /WR /RES GND VDD PS /RESET VDD VCC /OE R/W /CE FLASH D0 ~D7 A0~An GND Serial Interface (SPI) VDD VCC A0 A0 VCC C68 VDD OR VSS LCD PANEL PORT3_1 VDD MPU PORT2 PORT1 PORT0 /RES GND /CS1 CS2 SDI (D7) SCK (D6) SDO (D5) EPL43102 PS /RES GND /RESET Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 55 EPL43102 43 Com / 102 Seg LCD Driver 80-Family MPU VDD VCC A0 A1~A7 /IORQ A0 /CS1 CS2 VCC C68 EPL43102 DECODER 80 type MPU D0 ~D7 /RD /WR /RES GND D0 ~D7 /RD /WR /RES GND VDD PS /RESET 68-Family MPU VDD VCC A0 A1~A15 VMA A0 /CS1 CS2 VCC C68 EPL43102 VDD DECODER 68 type MPU D0 ~D7 E R/W /RES GND D0 ~D7 /RD /WR /RES GND VDD PS /RESET 56 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) EPL43102 43 Com / 102 Seg LCD Driver 13 Application Circuits Example 1: 42x102 pixels driving application circuits ("Single-chip" using internal oscillator) LCD PANEL 42X102 PIXELS COM0~41 CLS /IORQ A0 . . An SEG0~SEG101 FR CL /DOF V0 V1 DECODER MASTER ( EPL43102 ) V2 V3 V4 M/S D0~D7 /RST OSC /CS1 CS2 A0 /RD /WR A0 /RD /WR D0~D7 /RES RESET CIRCUIT Example 2: 43x204 pixels driving application circuits ("Multi-chip" using external oscillator) LCD PANEL 42X204 PIXELS WITH ICONS DISPLAY COM0~41+COMI SEG0~SEG101 CLS /IORQ A0 . . An FR CL /DOF V0 V1 FR CL /DOF V0 V1 V2 V3 V4 M/S SEG0~SEG101 DECODER MASTER (EPL43102) V2 V3 V4 M/S SLAVE (EPL43102) OSC /CS1 CS2 A0 /RD /WR D0~D7 /RST MPU OSC /CS1 CS2 A0 /RD /WR D0~D7 /RST CLK0 A0 /RD /WR D0~D7 /RES RESET CIRCUIT Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) 57 EPL43102 43 Com / 102 Seg LCD Driver 58 * Product Specification (V1.8) 01.20.2006 (This specification is subject to change without further notice) |
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